Recent developments in fast semiconductor memories are leading to high-speed signal transmission rates of, for example, up to 7 Gbit/second. These high signal transmission rates require careful design considerations with respect to the implementation of an appropriate topology and a suitable design of interface circuits such that these high signal transmission rates can be realized.
Future generations of memory systems will arrange the memory chips in a chip cascade or chip chain which aims to increase the attainable storage density. For this chaining of the memory chips, serial high speed interface circuits are required to include a repeater (re-driver) function.
The enclosed FIGS. 1A to 1D respectively show block diagrams of different architectures of the arrangement of semiconductor memory chips. FIG. 1A depicts a loop forward architecture of, for example, four semiconductor memory chips M1, M2, M3 and M4 on a memory module MMOD, wherein rank 1 is given to memory chip M1, rank 2 to memory chip M2, rank 3 to memory chip M3 and rank 4 to memory chip M4. Write-/command and address signals WR/eCA are transmitted through a write data-/command and address signal bus from a memory controller C to the first memory chip M1 and from there to one or more of the following memory chips M2, M3 and M4, and the read data RD are transmitted separately through a read data bus from one or more of the memory chips M1 to M4 to the memory controller C.
FIG. 1B depicts another possibility of arranging the chain of memory chips M1 to M4 on the memory module MMOD in a shared loop for the write data-/command and address signals WR/eCA and the read data signals RD.
Both architectures depicted in FIGS. 1A and 1B have following common characteristics: the propagation time for WR/eCA and RD is matched by the structure; the sum of the propagation times is constant for each rank; read data RD of each rank inserts natively; and the system calibration is quite simple.
FIG. 1C schematically shows a further architecture in which four semiconductor memory chips M1 to M4 attached on a memory module MMOD are arranged in a loop back architecture, wherein the write data-/command and address signals WR/eCA are transmitted via a write data-/command and address signal bus to one or more of the four memory chips M1 to M4 in one direction (from the memory controller C to the right) and the read data RD are transmitted from one or more of the four memory chips M1 to M4 to the memory controller C in the inverse direction (i.e., from right to left in FIG. 1C).
Another possible topology, namely the star topology is depicted in FIG. 1D. A first memory chip M1* on the memory module MMOD is a dedicated master memory chip and has a re-drive function for the write data-/command and address signals WR/eCA on a write data-/command and address bus to the other memory chips M2 to M4 on the memory module which are connected to the master memory chip M1* in a star topology. The master memory chip M1* must have a re-drive function for read data RD sent from one or more of the memory chips M2 to M4 for transmitting the same to the memory controller C.
The fundamental characteristics of both topologies, namely the loop back architecture shown in FIG. 1C and the star topology shown in FIG. 1D are: the total propagation time for the write data-/command and address signals and for read data is different for each rank; read data insertion is sophisticated; the total delay is depending on PVT; and the system calibration is difficult.
FIG. 2 shows more details of a memory module MMOD on which are attached four memory chips M1, M2, M3 and M4 to which rank 1, rank 2, rank 3 and rank 4 are respectively associated. The memory chips M1 to M4 are arranged in a loop forward architecture and connectable to a memory controller C (not shown). FIG. 2 schematically shows that each memory chip M1 to M4 includes a first interface circuit section I1 for receiving and transmitting write data-/command and address signals from the memory controller C through a write data-/command and address signal bus to one or more of the memory chips M1 to M4, and each first interface circuit section I1 includes a transparent write data-/command and address signal re-driver/transmitter path. Each memory chip M1 to M4 further includes a second interface circuit section I2 connected to a read data bus RD for transmitting read data signals from one or more of the memory chips M1 to M4 to the memory controller C. Also the second interface circuit section I2 includes a transparent read data re-driver/transmitter path. FIG. 2 further shows a clock signal bus CLK for receiving, for example, from the memory controller a clock signal CLK (reference clock) and transmitting the same to a memory core MCORE of each memory chip M1 to M4 and from each of the memory chips M1, M2, M3 to the respectively next adjacent memory chip.
As mentioned above for the loop forward architecture shown in FIG. 1A, the propagation time of the write data-/command and address signals WR/eCA and of the read data signals is matched by the structure, the sum of the propagation times is constant for each rank, the read data of each rank inserts natively and the calibration of the system is quite simple. The block diagram of FIG. 2 further shows that the transparent signal path for write data-/command and address signals WR/eCA and read data RD, respectively, are fully transparent for the memory controller C. Further, the memory controller cannot localize any arbitrary placement of a memory chip on the line and each rank shows a fully equal timing.
For a memory system design of a memory module as it is shown in FIG. 2 there are the following objectives: same propagation direction; same propagation delay for each rank; same latency for each rank; no functional cause of collision of read data; and the timing calibration at the memory controller C should be simple.